Design Compiler Tutorial 2021: Synopsys

# Define the target technology library (the standard cells you are mapping to) set target_library slow.db

write -format verilog -hierarchy -output "my_design_netlist.v" write_sdc "my_design_final.sdc" Use code with caution. Pro-Tips for 2021 Synthesis: synopsys design compiler tutorial 2021

# Verilog netlist for downstream tools write -f verilog -hierarchy -output outputs/rv32i_core_synth.v # Define the target technology library (the standard

# Create a clock named 'clk' with a period of 10ns (100MHz) create_clock -name clk -period 10 [get_ports clk] synopsys design compiler tutorial 2021

The basic design flow using Synopsys Design Compiler involves:

Check if any paths were ignored or if there are "unconstrained" paths.