Modern FPGAs contain dedicated hard-blocks called DSPs (Digital Signal Processors) specifically designed for multiplication and accumulation. These blocks can perform $18 \times 18$ or $27 \times 18$ multiplication in a single clock cycle at very high frequencies (often > 300MHz).
error_count = 0;
input signed [WIDTH-1:0] a, b; output signed [2*WIDTH-1:0] product; 8bit multiplier verilog code github
Extremely low area (one adder plus registers). Cons: Requires 8 clock cycles to produce a result. 300MHz). error_count = 0
// Powers of 2 #10 A = 8'h01; B = 8'h01; #10 check_result(1, 1, 1); input signed [WIDTH-1:0] a