The Art Of Analog Layout By Alan Hastings | Portable

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Mastering the Portable Wisdom of The Art of Analog Layout by Alan Hastings If you’ve worked in IC design for more than a week, you’ve heard the name: The Art of Analog Layout by Alan Hastings. It’s the bible of physical design for analog and mixed-signal chips. But lugging a 600+ page textbook to your desk isn’t practical. Here’s a portable summary of the core principles you can apply immediately—whether you’re a student, a layout engineer, or a circuit designer reviewing for tapeout. 1. Matching: The Heart of Analog Layout Hastings drives home one truth: absolute values don’t matter; ratios do .

Common centroid – For critical differential pairs (e.g., input pairs in op-amps), use interdigitated or common-centroid layouts to cancel linear gradients. Dummy devices – Add dummy resistors/transistors at array edges so every active device sees identical etch and STI stress. Orientation – Keep all matched devices oriented the same direction (no 90° rotations).

Portable takeaway: If you need two transistors to match 0.1%, draw them as four interleaved fingers, not two separate rectangles. 2. Parasitics Aren’t “Just Wires” In analog, every interconnect has resistance, capacitance, and inductance. the art of analog layout by alan hastings portable

Metal migration – Hastings warns: wide enough metal for current, but not so wide you add unnecessary cap. Shielding – Run sensitive analog signals between grounded metal lines. Clock lines go far away or orthogonal. Substrate coupling – Use guard rings (p+ for NMOS, n+ for PMOS) and deep n-wells to isolate noisy digital blocks.

Portable takeaway: Before routing, ask: “What is the most sensitive node?” (often the input pair or feedback node). Shield it first. 3. Device Physics in Layout Terms Hastings translates semiconductor physics into layout rules you can see.

WPE (Well Proximity Effect) – Keep transistors away from well edges by 2–3 µm to avoid threshold voltage shifts. LOD (Length of Diffusion) – STI stress changes mobility. Use the same diffusion length for matched devices. Salicide blocking – For high-resistance polysilicon resistors or low-current paths, add a silicide-block layer. I understand you're looking for a blog post

Portable takeaway: Don’t just DRC-clean your layout – check for identical environments around matched devices (same number of contacts, same dummies, same well distance). 4. Practical Floorplanning for Real Chips Hastings isn’t just theory. He gives actionable floorplan advice:

Signal flow – Place blocks to follow the schematic hierarchy. Don’t make current mirrors run across the whole chip. Power/ground – Star routing for sensitive analog supplies. Separate analog and digital grounds (tied at one point only). Decoupling – Place 0.1–10 pF MOM caps right next to high-current stages.

Portable takeaway: Start layout by placing the input differential pair and current mirror first. Everything else goes around them. 5. Verification Isn’t an Afterthought Hastings emphasizes: “If you didn’t check it, assume it’s wrong.” Here is the blog post: Mastering the Portable

LVS – Match netlists exactly. Floating nodes are fatal. PEX – Post-layout extraction often reveals a hidden 50 fF cap that kills bandwidth. Antenna rules – Jump up/down metal layers to avoid gate-oxide damage during plasma etch.

Portable takeaway: Run LVS after every major routing step, not just at the end. Final Portable Checklist (from Hastings’ philosophy) ✅ Matched devices: common centroid + dummies + same orientation ✅ Sensitive nodes: shielded, short, and away from noise ✅ Substrate isolation: guard rings around everything noisy ✅ Parasitics extracted and simulated ✅ Environment identical for matched devices The Art of Analog Layout is deep, but its portable core is simple: copy the environment, cancel gradients, and always think about what you can’t see (parasitics). Keep this list on your desk. Tapeout with confidence.